Continuing on with wireless communications related subjects.  The architecture of a UMTS systems is the first thing to begin understanding if you want to undertake an education such as this.  It consists of three distinct components:

1. The User Equipment (UE)
2. The UMTS Terrestrial Radio Access Network (UTRAN)
3. The Core Network (CN)

As with any wireless network out there, the main purpose is the provide access to services (data, voice, etc.)  The services network is divided into Public Switched Telephone Network (PSTN) that provides voice and special telephone related services (look it up on wiki), and the internet, which provides a wide range of packet data services such as email or access to the world wide web.  These things are probably all sounding very familiar to you, and they should, because they are critical in maintaining today’s society, and almost everyone living in the modern world uses at least one of these services sometimes in their daily lives.

The UMTS mobile, also known as the User Equipment (UE), interfaces with the UTRAN via the UMTS physical layer radio interface.  In addition to radio access, the UE provides the subscriber with access to services and profile information.  For example, the cell phone you carry in your pocket is the UE (user equipment) that interfaces with the cell phone towers that companies like Verizon, AT&T, and Sprint provide for you.

In UMTS, there are two Core Network (CN) configurations, the Circuit Switched CN (CS-CN) and Packet Switched CN (PS-CN).  The CS-CN is based on the GSM Public Land Mobile Network (PLMN) and provides functions such as connectivity to the PSTN, circuit telephony services such as voice, and supplementary services such as call forwarding, call waiting, etc.  The PS-CN is based on the GSM General Packet Radio System (GPRS) PLMN, which provides access to the Internet and other packet data services.

Both core networks connect to the UMTS Terrestrial Radio Access Network.  The UTRAN has two options for its air interface operations.  One option is Time Division Duplex (TDD), which makes use of a single 5 MHz carrier for communication between the UE and the UTRAN.  The other option is the Frequency Division Duplex (FDD), which provides full duplex operation using 5 MHz of spectrum in each direction to and from the UTRAN.  The following articles in the wireless communication systems section  focus on the operations and design aspects of the UTRAN in FDD mode.

How do all of these components fit together?  Check out the image below.

UTRAN Components

The UTRAN consists of one or more Radio Network Subsystems (RNS).  An RNS consists of one Radio Network Controller (RNC) and several Nodes.  The radio network controller and the nodes are two essential components of UTRAN.  Apart from these two component types, UTRAN requires Operation Maintenance Centers (OMC) to perform Operation Administration and Maintenance (OA&M) functionality on the nodes and RNCs.  Yes, I know the acronyms are getting a little out of hand, but it is essential to learn them if you want to speak the language!  Engineers only speak to each other with acronyms and it is very very annoying indeed.

• Radio Network Controller: The Radio Network Controller is the master of UTRAN.  It handles all aspects of radio resource management within the radio network subsystem.  The UMTS chose to use it instead of the base station controller in order to stress the independence of UTRAN from the Core Networks (CN).  It interfaces with the core network components such as the Mobile Switching Center (MSC) and Service GPRS Support Node (SGSN) to route signaling and traffic from the User Equipment (UE).  The RNC also interfaces with other RNC’s within UTRAN to provide it with wide mobility (very important!)

• Nodes: Within this network, a node is the radio transmission and reception unit within UTRAN (remember above, I explained that the UE is your cell phone you carry in your pocket).  It handles radio transmission and reception for multiple cells within a coverage area.  So if you think about the amount of area that a certain cell tower (cell) can transmit its signal with the proper quality of service (QoS), you can get a mental grasp on multiple cells being in one coverage area, say if the towers are close together.  The node implements CDMA-Specific functionality such as encoding, interleaving, spreading, scrambling & modulation.  The nodes are also what used to be known as the Base Transceiver Subsystems (BTS) in second generation systems.

Hey!  This article has a simple purpose, to teach you basic functionality and terminology related to modern UMTS-CDMA digital coding techniques.  One swift read of this information-packed kick in the face will leave you trembling at the knees with curiosity for more.  Well, maybe not.  But the first step in the UMTS-CDMA system applies error correction techniques so that any errors at the receiver can be corrected.  Various techniques can be employed to prevent errors at the transmitter.  You have probably studied one or more of these in your days if your an electrical or computer engineering student, professor, or professional.  One of these techniques is the use of Forward Error Codes, which are applied to the data before it is transmitted via the physical layer.

It is known that wireless is an inherently error-prone medium in which to operate our delicate signals.  Therefore, many error correction techniques are employed.  In the UMTS-CDMA systems, due to the large bandwidth available, a variety of coding techniques are employed.  The following three error correcting methods come to mind:

Convolutional Encoding

Convolutional encoding provides the ability to correct errors at the receiver.  So, the errors are removed from the signal by the receiver via convolutional encoding.  As a result, lower transmission power is required, which can result in more errors.  Some amount of errors can be tolerated since they can be recovered through convolutional encoding.  The convolutional encoder encodes input data bits int output symbols.  The data bits are entered into the first register at each clock cycle and the data bit in the last register is dumped out.  Data bits are tapped at various positions and XORed to provide encoded bits.  It is typically used for voice and low data rate applications.  Here are the main points to keep in mind:

• Provides the ability to detect and correct errors at the receiver.
• 10^(-3)  BER, typically used for voice and low data rates.
• Uses history of bits to recover from errors.

Turbo Encoding

Turbo codes are a new class of error correction codes used in digital comm systems.  Turbo codes have been shown to perform better for high-rate data services (which is what we crave for) with stringent error rate requirements on the order of 10-6 Bit Error Rate (BER).  The turbo encoder consists of two constituent convolutional encoders.  Both constituent encoders use and code the same data.  The first one is fed data in the same order as the input data.  The second encoder uses a permuted form of the input data and the permuting is accomplished by the use of an interleaver, which will be discussed in detail in the following post(s).  Again, main points:

• 10^(-6)  BER, suitable for high data rates.
• Uses convolutional encoders in parallel to increase reliability.
• Increased delays but better error correction capabilities.

Block Interleaving

Block interleaving protects data against fading and prevents bursty errors (so imagine a sudden burst in the amplitude of a received signal, think that might saturate you and ruin your signal? You bet.)  This is accomplished by providing time diversity, where the bits are separated in time before transmission over the air.  This is typically used with FEC codes, since FEC codes are not well suited to handle these bursty errors.

• Method to shuffle bits to prevent errors during deep fade.
• Provides time diversity.

All of these techniques will be described in detail, separately, in the following three articles.

Jeff

There are several different types of 3G wireless technologies that are defined and planned to be up and working today.  There are also several that are on their way.  These are successors of course, to the previous 2G technologies that dominated the airwaves.

CDMA2000

CDMA2000 is the successor to IS-95 systems.  CDMA2000 provides a definition for two different options for 3G technologies.  IT Differs in the amount of the frequency spectrum that is used.  The Spreading Rate (SR1) operates in the 1.25 MHz band and is known as a 1x system.  Another proposal exists also which is referred to as 1xEV-DO.  The 1xEV-DO (1x Evolution for Data Optimized) solution is a data-only solution that enables a bandwidth of 2Mbps without any mechanism for voice.  This is the type of data rate that we are all familiar with, the 3G 2Mbps speed of data connection.

The Universal Mobile Telecommunications System (UMTS)

The Universal Mobile Telecommunications System (UMTS) is a successor to GSM/GPRS systems.  There are also two options for the UMTS networks.  The Frequency Division Duplex (FDD) option uses spectrum bands which are paired together.  For example, two different 5 MHz bands are used for uplink and downlink.  The Time Division Duplex (TDD) option uses an unpaired band.  In other words, the same 5 MHz band is shared between uplink and downlink for TDD.

Universal Wireless Consortium for IS-136 systems

The UWC-136 (Universal Wireless Consortium for IS-136 systems) was originally considered to be the evolution for IS-136 systems.  However, the IS-136 system operators eventually decided to follow the path of CDMA2000 or UMTS.

Why did we need 3G Technology?

Back in the late 1990′s, when most of the readers out there were still playing in the sandbox, the International Telecommunication Union (ITU) set the requirements for the next generation of wireless networks (that is why they are called Third Generation (3G)).  One of the many many requirements is to reach peak data rates of at least 2 Mbps.  This is more relvant to the Downlink since the majority of traffic comes from the server to the client in the Internet World.

To meet this new high speed requirement, the 2nd generation wireless networks came up with several different evolutions before eventually being replaced.  The GSM evolution includes GPRS and EDGE, which provide packet data services and represent intermediate solutions until a UMTS Release 99 System is deployed.  The 1xEV-DO is one possible evolution path from 1xRTT, and HSDPA is a Release 5 feature of UMTS.

So how did UMTS Evolve?

UMTS is the network of choice these days.  Yes, UMTS is 3G…If you haven’t caught that yet.  For those nerds out there that are curious, the evolution of UMTS has progressed over the years in the following fashion:

UMTS Release 99

• 2 Mbps theoretical peak packet data rates
• 384 kbps (practical)

UMTS Release 5

• HSDPA (14 Mbps downlink theoretical)
• IMS (IP Multimedia Subsystem for multimedia)
• UP UTRAN (for scalability and lower cost)

UMTS Release 6

• HSUPA (up to 5.76 Mbps uplink)
• MBMS (Multimedia Broadcast Multicast Service)

UMTS Release 7

• Multiple Input Multiple Output (MIMO) Antenna Systems

Cellular systems have come a long way since their introduction in the 1980s.  The evolution progressed from First Generation (1G) systems to Second Generation (2G) systems.  Now, Third Generation (3G) systems are being deployed.

1G systems introduced the cellular concept, in which multiple antenna sites are used to serve an area.  The coverage of a single antenna site is called a cell.  A cell can serve a certain number of users, and higher-system capacity can be achieved by creating more cells with smaller coverage areas.  One distinguishing factor of 1G systems is that they make use of analog radio transmissions, so user information, such as voice, is never digitized.  As such, they are best suited for voice communications, since data communications can be cumbersome.

The migration of 1G analog technologies toward 2G technologies began in the late 1980s and early 1990s.  The primary motivation was increased system capacity.  This was achieved by using more efficient digital radio techniques that enabled the transmission of digitized compressed speech signals.  These digital radio techniques also supported data services with data rates as high as 14,400 bits per second (14.4 kbps) in some systems.  2G data communication is typically done using circuit-switched techniques, which are not very efficient for sending packet data such as that sent on the Internet.  This inefficiency makes the use of wireless data more expensive f or the end user.

The next step in the evolution is from 2G to 3G, which started in the year 2000.  The new key feature of 3G systems is the support of high-speed data services with data rates as high as 2 million bits per second (2 Mbps).  Data can be transferred using packet-switching techniques rather than the circuit-switching approach.  Therefore, it is more efficient and less expensive.  This opens up the possibility of cost-effective Internet access, access to corporate intranets, and a host of multimedia services.

If you want to read more about the evolution of wireless networks and WCDMA radio networks in general, please stay tuned for the next several editions where I will go into details.

Upcoming including but not limited to:

• Physical layer functions
• W-CDMA Channels
• Basic call setups
• Data session setups
• Service reconfigurations
• UTRAN mobility management
• Inter-system procedures
• RF design & analysis of UMTS radio networks
• The evolution of UMTS
• Architectures

If you prefer using the features of an Android operating system but are stuck with an iPhone or any other iOS for that matter then you are not completely out of luck.  There are several things you can do to make the features on your iPhone work like Android features.  Here are some tips and tricks found on lifehacker that we will pass on and share.

Locking up your iPhone screen widgets

customizing your iPhone home screen is actually much simpler than it would appear.  Follow the directions in this article in order to customize your iPhone lockscreen features.  There you will find a nice set of instructions for setting up a custom lockscreen that is simple, sleek, and provides you with time and date and other simple things that you need when looking at your phone at a quick glance.

Unobtrusive Notifications

iOS seriously fails at handling notifications. No matter what kind of notification you get, iOS gives you the same annoying blue dialogue box that interrupts whatever you’re doing. Tired of  these?   MobileNotifier is an excellent solution.  This is a jailbreak hack, so you’re out of luck if you’re sticking with a jailed device. If you need a reason to jailbreak, this is a good one.

MobileNotifier handles notifications similarly to the way Android does—by keeping them in an always-accessible drawer and by notifying you without interruption so you can continue doing what you’re doing. When you receive a text message, for example, a little bar will pop up top to let you know that you’ve received a notification. You can leave it up there for as long as you need and dismiss it (or act on it) whenever you want. To see all of your notifications (or to clear them), you just need to double tap the home button and you’ll see your notifications drawer (as well as multi-tasking mode). If you’d like to set up MobileNotifier (and you should), follow these instructions on Lifehacker.

Getting Google Apps on your iPhone

Here are some Google Apps that you can get on your iPhone:

• The official Google Mobile App
• Google latitude
• Google Earth
• Google Voice
• GoogleReader (use Google  docs?  Super useful and worth the $5 or so that it costs)

You may prefer to use the mobile webapps provided by Google over the original options, so make sure you put them on your iOS and bookmark them if you do.  Just make a bookmark on your homescreen that links to them.

Turn on Google Sync

So you’ve never been able to do this before, but now there is a way.  Google Sync for iOS will let you push your contacts, calendars, and mail to your iOS device and it’s really easy to set up. It’s almost identical to setting up MobileMe, except it uses the Microsoft Exchange protocol. Google Sync requires iOS 3.0 or higher, but iOS 4.0 or higher will let you add multiple Exchange accounts (so you’ll want to make sure you’ve upgraded if you need multiple Exchange accounts on your device). If you want to get Google Sync set up, Google has some instructions here: Setting up Google Sync. Once you have it up and running, you’ll have your Google data pushed and syncing over-the-air to your iOS device just like you would with Android.

Improving Voice Recognition

iOS’ VoiceOver is what it is. For some it’s helpful and for others (like myself) you just forget it even exists until you accidentally hold down the home button for too long. While there aren’t any great improvements to iOS’ voice recognition capabilities, there are two things that can help. First, if you haven’t already download the you should, if only for its voice search capabilities. Additionally, you want to get your hands on a copy of the Dragon Dictation app, which will let you create notes as well as send email and SMS text messages with your voice. Both apps are free in the iTunes App Store so you really have every reason to give them a shot.

Software circular buffers are data structures used to pass data from one section of code to another, where the code sections usually have no other interaction with each other. One situation that dictates that a “buffer” be used is when it is possible that a burst of data to occur that exceeds the “processing” codes ability to keep up on an item by item basis. Then a separate section of code to buffer (accept from the external source and insert it into a circular buffer) is necessary.

On average, the processing must keep up, or no amount of buffering will prevent an eventual overrun and loss of data. Another situation where you might use a “buffer” is to compartmentalize the functions of your code. For example, if you are using a keypad on a project, you may choose to write one section of code that detects that a key has been pressed, determines what it is, and places the ASCII code for it in a circular buffer.

A completely separate section of code could then process the “stream” of key-presses for the purpose at hand, say a combination lock code. Partitioning the code in this fashion not only makes each section easier to write (each is smaller and you get to focus on a simpler task), but also makes each section more reusable. The combination decoding could easily be used virtually unchanged with the code sequence coming from the SCI instead. The proper view of data in a circular buffer is a “stream” of sequential data items, often characters.

The section of code that sends data to another section inserts each new datum item into the buffer. In general, that code inserts data as fast as it becomes available. The section of code that receives the data removes each item from the buffer.  The receiver almost always has some processing task to perform on the received data items, and often processes at a slower instantaneous rate than the insertion code. It is often the case that several circular buffers will exist within a program. It is also often the case that the sending and/or receiving code sections are in interrupt handler routines. A possible point of confusion is that any receiving ISR routine (say an SCI receive ISR) will probably play the role of sender via the circular buffer. Virtually the only SCI receiver ISR I have ever written was to have it read the incoming characters and place them in a circular buffer, and nothing more.

How Do Circular Buffers Work?

A circular buffer is really a linear sequential buffer that is used from beginning to end, over and over. Unlike a STACK which operates as a first-in-last-out (FILO) buffer and naturally keeps reusing memory as items are popped on and later pulled off of the stack, with a circular buffer one must work at reusing memory. This is accomplished by having code to wrap around to the beginning of the buffer whenever the next location gets past the end of the buffer. Picture the buffer as a consecutive set of memory locations that has its last location adjacent to its first location (in effect a circle).

This circular buffer forms an endless queue. The queue functions as an endless first-in-first-out (FIFO) buffer. It is indeed endless as long as the process receiving the data never gets a complete buffer length behind the one sending the data. An evaluation of how far behind the receiver may get is the only way to determine the size one needs for the buffer. If it never gets more than one data value behind then a 2-long buffer is sufficient. If it gets up to 99 behind then a 100 element buffer is needed, and so on. In addition to the memory for the buffer itself, essentially an array of data, a circular buffer requires two markers, one to tell where to insert the next datum and one to tell from where to extract the next datum. Note that a stack required only one marker (called the Stack Pointer). The two markers can take either of two forms – indices or pointers.

Either type tells the next available location to place new data into the buffer and the next location containing data to be taken out of the buffer. If the buffer is four bytes long, an index would have a value from 0 to 3, whereas, a pointer would contain the address from buffer to buffer+3. The out marker chases the in marker around the buffer. Whenever it catches up it means the code receiving data has caught up with the code sending data and so the buffer is empty (has no more data to process at the moment). There is never a conflict between the two code sections in updating the markers as in marker is only updated (incremented) by the code inserting the buffered data, and out marker is only updated (incremented) by the code extracting the data.

Common Uses for Circular Buffers

Probably the most common use of a circular buffer is for storing characters received from an input device. The interrupt handler for the device simply reads the device (usually whenever an interrupt occurs indicating new data has been received), places it in a circular buffer, and exits (returns from the interrupt). There are numerous other uses for circular buffers and no assembly language programmer or high-level language programmer (especially one working with real-time or event-driven systems) should be without this powerful software tool. To implement a circular buffer in any language you need four distinct code sections. First, you must declare the buffer and the two pointer variables that will be used with it. In HCS08 assembler that section will look like this:

There also needs to be an initialization section that is executed before the buffer can be used and must be executed only once in your program. This should exist with the code that is executed almost immediately after reset on any embedded system that uses such buffers. In HC11 assembler it could be:

So if we are using our circular buffers to move data between a sender and a receiver we will need to make a few subroutines to implement our buffers.  The next two sections of code are in (or are in a subroutine called by) the sender or receiver, respectively. I will first show example code for buffers containing single byte data values. (The previous examples are independent of data item size.) The examples are in subroutine form.

If the data items are more than one byte then something more than an sta or lda is needed to add or retrieve them, and more than a single increment is needed to advance the pointer in the buffer. Those are the only two changes.

I hope you enjoyed learning about circular buffers! They are truly wonderful.

This article gives another step-by-step lesson about assembly language programming.  In order to follow along with this article, you should have this previous article on hand:  An Assembly Language Example

Refer to that program and do the following:

Rewrite step 3 above using 32 and 96 instead of C6 and C7.

This sounds like a good idea at first. Only about half the number of instructions will be needed as we move 2 bytes at a time instead of one. But wait! How do we move an odd number of bytes? We can’t move only the 5th byte using these two instructions. For this exercise it is not fair to revert back to the previous instructions for the 5th byte (although in an actual program that would be a very good idea). Read the code below to find out!

E425: 32 E24E                              load H:X from ni[0-1]
96 0188                                           store H:X into n[0-1]
32 E250
96 018A
32 E251
96 018B

This is expressed more cryptically in a simulator/debugger memory display, but is the same info:

E420: .. .. .. .. .. 32 E2 4E
E428: 96 01 88 32 E2 50 96 01

E430: 8A 32 E2 51 96 01 8B ..

Another Assembly Language Task:

Perform I = 3*J – K + 21, where I, J, and K are variables. We will need some new instructions. They are:

CB hh ll Add value at location hhll into A
C0 hh ll Subtract value at location hhll from A

Step1. Decide where to place I, J, and K in memory. Remember they must be in RAM.

019E: ?? Location for I showing its value is unknown
019F: ?? Location for J
01A0: ?? Location for K

Usually we just place all our variables in consecutive RAM locations.

Step2. Decide where in memory to place the constant 21. It must be in ROM.

E0E0: 15                        Note the value looks different in hex!

Step3. Decide where to place the program and write it.

E10C: C6 019F                    load A with value from J
CB 019F                                add in another J to form 2*J in A
CB 019F                                add in another J for 3*J
C0 01A0                              subtract K from 3*J in A
CB E0E0                              add the constant 21 into A
C7 019E                              store the result into I

Step4. Define the starting address in the reset address in ROM.

FFFE: E10C

You should enter these values in the S08 simulator memory, and run the program a couple of times. REMEMBER to enter test values into the variables J and K before running the program. This section of code assumes that those values get placed there by sections of code not shown. To test this section you must provide some values to test. Verify that the value stored into I by the last instruction is correct for the values of J and K that you provide.

Assembly Language Example

Okay, so this post is just an example of an elementary assembly language program.  It will be useful to you if you haven’t learned how to program in assembly before, or simply want to learn some syntax.  This article specifically talks about the HCS08 microcontroller, so if you want to compile this code, you should have one of those handy.  Also, make sure you have the databook on hand.

We are now ready to write our first machine language program. This program is to initialize a 5-byte variable (an array that I will think of as being named n) by copying a 5-byte constant (an array I will think of as being named ni) into it. There are several steps that must be taken – it is very important to understand what each step does and how it fits into the programming picture.
Step 1. Decide where in memory the array variable (n) will be located. It must be in RAM so all five must be between addresses 0060-025F. All five must be in succession for it to be an array. Lets pick 0188-018C. If asked for the address of n, the correct answer would be 0188 (the lowest number in the set of addresses). There is nothing more to do for any variable other than to decide on its address.

Step 2. Decide where in memory the array constant (ni) will be located and what values it has. Constants must be in ROM so all five must be between addresses E000-FFFF (actually about FFAE is upper limit). I will select location E24E-E252. Many constants have self-defining values. Suppose we needed the constant five. Its value would be 5. The values I am about to choose for ni are not self-defining. I will select the ASCII (ASCII is a character code for alphanumeric information) value of the letters A to E. These decisions can be expressed as follows:

E24E: 41 42 43 44 45
Step 3. Decide where in memory to place the program, and write it. It also must be in ROM. I choose E425 to start. We will see where it ends. Here it is:
E425: C6 E24E load A from ni[0]
C7 0188 store A into n[0]
C6 E24F
C7 0189
C6 E250
C7 018A
C6 E251
C7 018B
C6 E252
C7 018C                     store A into n[4] – last byte of n
Question: What is the address of the last byte of this program segment?
Step 4. Tell the HCS08 to start at location E425 when power is first applied to it. We do this by defining a pointer constant with that value at location FFFE. We will discuss this reset location later in another article. For now all you need to know is that at power-on the value at location FFFE is loaded into the PC (because the PC is 16 bits, the value at FFFF contains part of the starting address as well.

FFFE: E425

Our first machine language program is finished. You can bring up the S08 simulator, type all of the values specified for the ROM into it – 5 bytes of data, 30 bytes of program, 2 bytes of reset address – press the reset icon and then single step repeatedly to watch it run. The above steps must be performed for every machine-language and every assembly-language program that you write with the HCS08.

Here are some blank maps of different countries and continents around the world.  I’ve found them useful on several different occasions.  Enjoy!

Blank Map of The World

Blank Map of The United States

Blank Map of South America

Blank Map of Russia

Blank Map of North America

Blank Map of Middle America

Blank Map of Japan

Blank Map of Europe

Blank Map of China

Blank Map of Australia

Blank Map of Asia

Blank Map of Africa

So this post is a little out of the ordinary, however I figured this nice rant about the history of computer technology may be useful to some readers out there.

The History of Computer Technology

The first computer built in America was the IAS computer. It was developed at the Institute for Advanced Study at Princeton under the direction of John Von Neumann between 1946-1950.

This obsolete machine’s architecture is presented not just for its historical significance, though that would be reason enough. Details about it are presented because many (most) modern computers (including the HCS08) trace their ancestry to the IAS machine. Those that do are referred to as von Neumann (or Princeton) architecture machines. The IAS architecture is relatively simple and is a convenient starting point for assembly language programming. An assembly language program for the IAS (though programs for it were written in machine language) would not look very different from modern load/store style machines. Also, a sense of the relative importance of concepts results from learning the IAS architecture. Programs written in a carefully selected subset of the HCS08 instruction set would look almost identical to an IAS assembly program (were we to create an assembler for that machine). We will then see how the complete HCS08 instruction set improves on the IAS instruction set and addressing scheme. The general design of the IAS machine is given below. The HCS08 is almost identical to it.

As originally designed (to cut costs the machine was built with less memory), the memory consisted of 4096 40-bit words. The number of words in computer memory systems (at least the maximum memory) always consists of a power of two. This is because the specific word in memory to be accessed at any given time is specified by a set of binary valued wires or lines called the address bus. The number of different locations in memory such a bus can specify is simply all the possible combinations of the two values possible on each of the lines. For an n-bit bus, that value is 2n. The address bus size for the IAS memory was therefore 12 providing for 212 = 4096 unique memory locations. The number of bits per word is up to the computer designer. Memory word sizes of 4, 8, 12, 16, 18, 24, 32, 36, 40, 48, 60, and 64 have all existed for some computer. Almost all computers made today use 8-bit memory words, although they all support data types that use several consecutive memory words together as a single value. Most desktop (or larger) computer systems support 8-bit, 16-bit, 32-bit, and 64-bit values. Some even support 128-bit values. Note, all of these sizes are multiples (in fact powers of 2 multiples) of the basic 8-bit word size so these values use 1, 2, 4, and 8 (some even 16) words, respectively. Whatever the memory size, anyone with some programming experience taking their first look at the memory system in a computer design, should think of the memory as an array with 2n elements. The address bus carries the value of an n-bit unsigned index into the memory array. The data bus returns (or supplies if a write instead of a read is issued) the m-bit memory word value of the specified element, where m is the word size (in bits) of the memory system.

The REGS component of the general design represents the register set used by the CPU (Central Processor Unit). Registers are fast special-purpose memory separate from the main memory. They support the fetching and execution of instructions stored in memory. The registers in the IAS design are given below:

IAS Instructions and Data

The IAS computer embodied the concept of a stored-program computer. The main memory contained two main categories of information – instructions and data. It is the ability to place different sequences of instructions in the memory that makes the computer so useful – it is what makes it a general-purpose computing device rather than a special-purpose or single-function computer. Instead of being constrained to building computers that perform only predefined single tasks (or small set of tasks), we can build a computer that does different tasks at different times. Such a computer can be reconfigured (reprogrammed) at any time to perform a new or different task. Often an important task is not even conceived of at the time the computer is designed. For the IAS machine, it was important that the programs and data shared the same memory. That way the instructions themselves could be processed as other data values. Self-modifying programs were the only scheme that the IAS designers thought of for performing loops that worked on different array elements each time through the loop. Between iterations of the loop, the instructions that accessed the array element were loaded into the AC and a value added to them to change the address portion of the instruction to the next array element to be processed. The modified instruction was then stored back in its memory location for execution the next time through the loop. Computer designers have since come up with several methods of accomplishing this type of operation without modifying the instructions themselves. Today, self-modifying code is considered taboo, as it is prone to logic errors that are hard to discover, cannot be executed out of Read-Only Memory (ROM), and other deficiencies that are beyond this article.

IAS Instruction Sets

The IAS instructions consisted of 20 bits – a 12-bit address and an 8-bit operation code (opcode). The operation code part specified both an operation and a register. The instruction’s 12-bit address part usually specified an operand by giving the memory address of the memory word involved in the operation. Basic operations like load (copy a value from a memory word to the implied register), store (copy a value from the implied register to a memory word), add (add the value in a memory word to the value in the AC replacing the AC value with the sum) are referred to as memory-reference instructions and form the core instructions for both the IAS machine and the HCS08 microcontroller. When an instruction contains the actual full address of the operand, as the IAS memory-reference instructions did, the value is usually referred to as a direct address and those instructions are said to use the direct addressing mode. Unfortunately, Freescale’s terminology for the HCS08 refers to such instructions as extended addressing mode instructions, and uses direct addressing mode to mean something else. The IAS instruction set had only one other class of instructions which were called register-reference instructions. Such instructions were said to use the inherent addressing mode. The HCS08 also has many such instructions and also refers to them as inherent addressing mode instructions. It is almost an oxymoron to say these instructions have an addressing mode as they use no memory address at all. Such operations involved only the registers. An example of such an instruction for the IAS machine was to add the value in the MQ to the value in the AC replacing the value in the AC with the sum. At this point we should note that descriptions of computer instructions usually shorten the phrase “the value in the Register-name” to just “Register-name”. Thus we describe the above addition as adding MQ to AC. It is implied that we mean the value in or content of the registers, and that by adding “to” we are replacing the original value after it is used in the operation with the result of the operation. An example of a similar instruction in the HCS08 instruction set is the “mul” instruction. It means multiply X times A, where X and A are HCS08 registers, replacing the value in the X:A pair with the 16-bit product.

Normally, instructions are executed in the sequence they appear in memory with the instruction in Memory[i+1] being executed immediately following the execution of the instruction in Memory[i]. The CPU register that keeps track of where the next instruction is located is the PC. Its name come from the fact that it is an index into the Program and that its normal mode of being modified is to be incremented (so it Counts) after each instruction. On the IAS machine each instruction occupied only half a word so the PC was incremented after every other instruction. There was an additional Register bit that told whether the current instruction was in the first or last half of the word referenced by the PC. On the HCS08 instructions take from one to four memory words, so its PC may be incremented several times per instruction.

Branch (jump) Instruction

A different type of instruction from those that manipulate data is the branch (or jump) instruction. They are so named because they cause the CPU to deviate from the normal sequence of instructions. Instructions in this class change the value of the PC from its normal incrementing sequence by loading a new value into it in much the same way that the loading of other registers work. A big difference, however, is that branch and jump instructions usually come in both unconditional and conditional varieties. The unconditional ones always change the course of execution from the normal sequential order, the conditional ones, however, may change it or they may let the normal order continue. Which program path occurs usually depends on the outcome of some previous operation such as subtracting one value from another. The IAS’s conditional branch would change the normal sequence if the result of the most recent arithmetic operation were positive, otherwise it would let the normal sequence continue. Conditional branching is the feature that gives computers the power to perform complex algorithms. Without it they would only be able to perform simple formula-based calculations! The HCS08 has a rich assortment of conditional branch instructions. Conditional branching is the feature that gives computers the power to perform complex algorithms. Without it they would only be able to perform simple formula-based calculations! The HCS08 has a rich assortment of conditional branch instructions.

Arithmetic Instructions

Data values in the IAS machine consisted of signed binary fixed-point numbers 40 bits in size. The sign used one bit so 39 bits remained to hold the magnitude of the value. The 39 bits are equivalent to about 12 decimal digits. As is true today, these fixed-point numbers could be considered to be integers or to contain fractional parts depending on where the binary point was considered to be. The hardware that performs calculations on the data works for a wide variety of conventions. Addition and subtraction require only that both operands are considered to have the binary point in the same position, there is no restriction on where it is considered to be. Multiply and divide don’t have even that restriction, but one must understand where the binary point of the results must be considered to be. Experimentation with decimal numbers with varying number of digits following the decimal point will allow one to understand the outcomes, and formulate the rules for properly placing binary points for the various computer operations. It should be made perfectly clear that no bits are used to indicate where the binary point is located; its position only exists in the way the programmer intends to interpret the value represented by the bits in the data word. Addition and subtraction instructions in the HCS08 support 8-bit unsigned and 2’s complement (signed) values. The multiply supports only 8-bit by 8-bit unsigned values – producing a 16-bit unsigned result. The divide instruction supports only a 16-bit by 8-bit unsigned divide, that produces an 8-bit quotient and a 8-bit remainder. By dividing the remainder by the original dividend, the quotient’s precision can be extended another 8 bits. This process can be repeated to any desired precision.

Indirect Addressing

The first architectural improvement in computers that eliminated the need to have self-modifying code was indirect addressing. This addressing mode makes use of a pointer data type. A pointer is a word (or multiple words if a word is too small) that has a value used as an address to another word in the memory. To specify an address indirectly, the indirect addressing mode instruction contains the address of a pointer instead of the data. The CPU knows that for such instructions there must be two memory areas accessed. The first reads the pointer and then uses its value as the address to access (read or write) the actual operand. To change the memory location accessed by such an instruction, the instruction itself need not be modified, only the value of the pointer variable. Few computers still use this form of indirect addressing, but rather its cousin, register addressing or a variation of it. In register addressing, the pointer value must be loaded into an address register with one instruction, and then that address used with another instruction. Again, to modify the actual data location a register addressing mode instruction accesses, one need only modify the value in the address register. The HCS08 has two such address registers, H:X and SP, although the SP main use is as a stack pointer. A variety of addressing modes based on those two registers are available.

Modern desktop computers now have many registers that can be used as accumulators and/or address registers. It is not uncommon for a computer to have 32 32-bit general- purpose registers that can be used for either. The HCS08 has only a microprocessor as its computing core, so it has only a single 8-bit accumulator and a pair of 16-bit index (address) registers – no general-purpose registers. In order to program in machine language assembly language or you must first learn the architecture of the computer you plan to program. The architecture of a computer specifies the registers in the CPU, the main memory size, and the instruction set (including not only the operations it can perform, but also all the addressing modes supported).

We are ready to study the architecture of the HCS08 microcontroller’s microprocessor core. The general design is given below. It is only a slight modification of the IAS one shown earlier. The only difference is that the Input/Output (I/O) devices are memory-mapped devices. That is, you access them as though they were normal memory, with load and store instructions within the main memory address space.

There are big differences with the details of the design. The register set is different, the memory size and shape are different, and the instruction set contains many more instructions. However, the basic functioning of the machines is very much the same. They both have the same load/store nature where most ALU operations must be performed on values in the CPU’s registers. They are both single address machines in that at most one of the operands of binary (two operand) operations (such as add) can come from main memory. (Actually the HCS08 has a very limited set of “move” instructions that transfer data from one memory location to another without going through a register.) The main memory can contain both instructions and data at virtually any location (even intermixed – although we will try not to do that). The CPU can operate on instructions as though they were data.

Memory Comparisons

Let’s check out the differences. The main memory of the IAS held 4096 40-bit values. The memory space of the HCS08 provides for 65536 8-bit values. Thus the HCS08 memory system uses a 16-bit address bus (216 = 65536) and an 8-bit data bus. The address bus carries information only one direction, to the memory system, but the data bus can carry information either to or from the memory (thus the double arrowheads on the data bus above). Not shown in the above diagram are control signals that tell the memory such things as whether a read or write is being performed. Each of the 65536 memory locations should be thought of as having an address and a contents (or value). The address is a 16-bit (4-hexadecimal-digit) number, while the contents is an 8-bit (2-hexadecimal digit) number. When we look at the instruction format we will find it is convenient that the value of an address can be stored exactly in two words of memory. In truth, that ability is the cause of the memory space being the size that it is.

At the risk of being too remedial, I will emphasize a possibly painfully obvious, but extremely important, concept. We often show the content of a section of memory by listing the memory address in one column and its content in another. Consider the example below. The left pair are in binary and the right in hexadecimal.

First, note how much more compact the hexadecimal (we’ll shorten that name as well, and start calling it hex) notation is. From this point on we will use mostly hex notation for address and values.

The key point I want to make is that only the value part is stored anywhere. The address is a fleeting number generated one at a time as needed and then its value disappears. When a program is being executed the Program Counter (PC) provides that value for instruction fetch. After each use of the PC it is incremented so the previous address value does not exist anywhere any more. The new value will exist only while it is being used to read the next word of the program.
Because the addresses are consecutive over an area of interest we often will show only the lowest address with a set of data values. By convention know that each successive memory content value is at an address that is one greater than the previous content. Thus the above set of memory values could be given as:
020D: 5B D8 74 06 31
A colon is often used to separate the address from a sequence of data values for added clarity. Here is my last restatement of the (hopefully blatantly obvious) address/data relationship – whenever the contents of locations 020D-0211 are given, the address part can never change, only the content can.

Byte Conventions

The HCS08 instruction set supports one 16-bit load operation. As 16-bit values require 2 words of memory, and the instructions specify only a single address, a convention must be established as to which of the two memory addresses that contain the 16-bit value will be specified in the instruction. It must also be decided whether the most-significant byte (MSB) or the least-significant byte (LSB) should be stored in the lower-numbered address of the pair. For me, this last question has an obviously best answer. Place the MSB at lower-numbered addresses. This convention is known as big-endian memory organization. When consecutive address values are written horizontally, the MSB will be to the left. This follows the standard convention for decimal numbers where more-significant digits appear to the left of less-significant digits. This convention, that more-significant bytes of multi-byte value be stored at lower address values, will never be violated in this course. In every situation that the HCS08 hardware dictates how they will appear, that convention is adhered to. In every situation where the programmer must decide, I will require that this rule be followed as well. Some machine designs even specify that two-byte values must start on an even address. Such requirements are referred to as memory alignment restrictions, but the HCS08 has no such restriction. The HCS08 always uses the address of the MSB, which is the lower of the pair. We will adopt that same convention, using the lowest address as the “handle”, for any program-defined groups of bytes for any size group that we create.

Registers to know

The Registers that you may need to know the most about are the ones in the Programmer’s Model as shown on Page 86 of the MC9S08QG Data Sheet for HCS08 Microcontrollers that is available in pdf form on the web and distributed in booklet form in class compliments of Freescale. The A register is an 8-bit accumulator used primarily for 8-bit arithmetic and load/store style moving of data. The H:X and SP register are used primarily for addressing. They are 16-bit registers so can point to any location in the memory space. The stack pointer (SP) exists primarily to support stack operations built into the hardware – we will learn all about these operations later. It is a 16-bit register as the stack utilizes main memory, and a 16-bit value allows the stack data to be placed anywhere in the memory space. The program counter (PC) tells where in the memory the next instruction to be executed is located. It is a 16-bit register so that instructions can exist and be executed out of any location in the memory space. The condition code register (CCR) keeps machine state information – our main programming use of it will be to guide conditional branch execution along the two paths that such instructions can direct a program. It is an 8-bit register.

This was wordy and didn’t necessarily wrap up completely but we have learned a lot of new information!  I hope you enjoyed this article about the history of computer technology and how this introduces you to how a simple computer called a microcontroller works.