# DC Biasing & AC Performance Analysis of BJT & FET Differential Amplifiers

## DC Biasing & AC Performance Analysis of BJT and FET Differential Amplifier Sub-circuits with Active Loads

Any op-amp worth its salt has a differential amplifier at its front end, and you’re nobody if you can’t design one yourself.  So, this article presents a general method for biasing and analyzing the performance characteristics of single-stage BJT and MOSFET differential amplifier circuits.  The following images show the general schematic for both kinds of differential amplifiers, often referred to as a differential input stage when used in designing op-amps.  Notice that these types of differential amplifiers use active loads to achieve wide swing and high gain.

Due to design processes and the nature of the devices involved, BJT circuits are “simpler” to analyze than their FET counterparts, whose circuits require a few extra steps when calculating performance parameters.  For this reason, this tutorial will begin by biasing and analyzing a BJT differential amplifier circuit, and then will move on to do the same for a FET differential amplifier.  But it should be noted that the procedures to analyze these types of differential amplifiers are virtually the same.

### BJT Differential Amplifier

The first thing needed is to configure the DC biasing.  To accomplish this, a practical implementation of $I_{BIAS}$ must be developed.  A very popular method is to use a current mirror.   A simple current mirror is shown below:

### BJT Current Mirror

It is easy to understand how a current mirror works.  Observe the equation governing the amount of collector current in a BJT, denoted $I_C$:

$I_C = I_S(e^{\frac{V{BE}}{nV_T}}-1)(1+\frac{V_{CB}}{V_A})$

where:

• $I_C$ is the collector current
• $I_S$ is the scale current
• $V_{BE}$ is the DC voltage across the base-emitter junction
• $V_T$ is the thermal voltage, typically 25 mV
• $n$ is the quality factor, typically between  1- 2 and is frequently assumed to be 1
• $V_{CB}$ is the voltage across the collector-base junction
• $V_A$ is the early voltage

Note: [This equation may look intimidating at first, but what is important to understand is that the point of designing “by hand” is to get close. One should aim simply to get a good estimation of such parameters as necessary bias current, gain, input impedance, etc.  In this way, computer simulations can analyze the hand-designed circuit in much closer detail, which greatly aids in the process of designing a real-life differential amplifier.  Knowing this, the equations to be used in this tutorial will be rough estimates, but are still invaluable when it comes to designing these types of circuits.]

By assuming a very large equivalent resistance, one can estimate that the collector current through any BJT can be described by:

$I_C \approx I_S e^{V_{BE}/V_T}$

What can be noticed here is that the only controllable variable in that equation is $V_{BE}$.  All the other terms in the equation are constants that depend on either the environment or the actual physical size of the device.  This means that for any two same-sized transistors, the currents through their collectors will be the same as long as the voltage across their base-emitter junctions is the same. By tying their bases and emitters together, we can mirror the currents between them!  In order to implement a successful current mirror, one transistor (here, $Q_5$) must have a current induced in it to mirror it to the differential amplifier’s current source (here, $Q_6$).  After adding this current mirror to our BJT differential amplifier, the resulting schematic is:

In order to properly bias this circuit, it is necessary to include $R_{BIAS}$.  Two things are accomplished by including $R_{BIAS}$ in our circuit.  One of them is that we can induce the current in $Q_5$, and thus, the current in $Q_6$.  The other important thing this resistor does is drop a majority of the available voltage across itself, so that $Q_5$ doesn’t have the entire voltage difference between the supplies across it!  To bias this circuit, the first thing one must do is determine what the desired magnitude of the current source will be.  This parameter depends on how you want the circuit to operate, and is usually a known value.  In this tutorial, we will assume we want an $I_{BIAS}$ of 1mA.  In order to determine the necessary size of $R_{BIAS}$, we analyze the loop that consists of:

$VCC \rightarrow I_{BIAS} \cdot R_{BIAS} \rightarrow V_{BE5} \rightarrow VEE$

Kirchoff’s Voltage Law (KVL) around this loop reveals:

$0 = -VCC + I_{BIAS} \cdot R_{BIAS} + V_{BE5} + VEE$

These kinds of circuits are typically supplied rails of $\pm 10$ to $15 V$.  So, this tutorial will assume:

$VCC = - VEE = 10 V$.

For a given technology, all of the BJT transistors are designed to have the same turn-on voltage. This tutorial will assume .7 V for each BJT.  That being the case, and rearranging the above equation, results in:

$R_{BIAS} = \frac{VCC - VEE - V_{BE5}}{I_{BIAS}} = \frac{10V - (-10V) - .7V}{1 mA} = 19.3 k\Omega$

By introducing a resistor $R_{BIAS}$ of $19.3k\Omega$ to the above schematic, the bias current is now established at 1 mA.  Due to symmetry, the currents through transistors $Q_1$ and $Q_2$ are each half of the bias current, described by:

$I_{C1} = I_{C2} = \frac{I_{BIAS}}{2} =\frac{1 mA}{2} = .5 mA$

Now that we know the collector currents through $Q_1$ and $Q_2$, characterizing the performance of this differential amplifier is a breeze.  Since the parameters we are interested in (gain, CMRR, etc) are small-signal parameters, the small-signal model of this circuit is needed.  To obtain this, a nice trick is to “cut the amplifier in half” (lengthwise, such that you only analyze the output side of the amplifier) to obtain:

Note: [even though the output signal is single-ended here, the output is still a result of the entire input signal, and not just half of it.  This is because the small-signal changes in the currents flowing through $Q_{2,4}$ are impeded from traveling down the branches controlled by current sources $Q_{2,6}$.  Also note that the connections between $R_{\pi}$ and the voltage-controlled current source (VCCS) indicate that the voltage that controls the VCCS is the voltage across $R_{\pi}$.  This is because the resistance in the emitter of these transistors has been omitted, due to its typically small value (10 to 25 $\Omega$).  In addition to this, $Q_6$ is assumed to be a small signal (AC) open-circuit.  The frequency response has also been omitted, and the amplifier is assumed to be unilateral.]

### Differential Mode Gain

It is simple to see that $v_{out}$ (the small-signal output voltage) is equal to the current across the parallel combination of the resistors $r_{o2}$ and $r_{o1}$ multiplied by the size of the same parallel combination.  Since we know the value of the current through this combination is equal to the input voltage multiplied by $g_m$ (the transconductance parameter):

$v_{out} =- g_mv_{in} \cdot (r_{o2} \| r_{o4})$

The transconductance parameter is a ratio of output current to input voltage. It is described mathematically as:

$g_m = \frac{\partial i_c}{\partial v_{be}} = \frac{\partial i_{out}}{\partial v_{in}}$

and can be solved for thusly:

$\frac{\partial I_C}{\partial V_{BE}} = \frac{\partial (I_Se^{\frac{V_{BE}}{V_T}})}{\partial V_{BE}} = \frac{I_Se^{\frac{V_{BE}}{V_T}}}{V_T} = \frac {I_C}{V_T}$

In this example, $I_C$ is .5 mA and $V_T$ is 25 mV.  With these values, we compute:

$g_m = \frac{I_C}{V_T} = \frac{.5 mA}{25 mV} = 20 \frac{mA}{V}$

Now that the transconductance parameter is known, the only other values needed to compute the differential mode gain are $r_{o2}$ and $r_{o4}$$Q_2$ is an npn transistor, while $Q_4$ is a pnp transistor, so they will not have the same small-signal resistance, but the procedure to find these two values are nearly identical.  The following equation describes the small-signal output resistance of any BJT:

$r_{o_{n,p}} = \frac{|V_{A_{n,p}}| + V_{CE}}{I_C} \approx \frac{|V_{A_{n,p}}|}{I_C}$

The parameter $V_{A_{n,p}}$ is typically given, and in this tutorial:

$V_{A_n} = 130 V$

$V_{A_p} = 50 V$

Which would result in:

$r_{o2} = \frac{V_{A_n}}{I_C} = \frac{130 V}{.5 mA} = 260 k\Omega$ and

$r_{o4} = \frac{V_{A_p}}{I_C} = \frac{50 V}{.5 mA} = 100 k\Omega$

Now that the small-signal resistances are known, along with the transconductance parameter, the differential mode gain ($A_{v,DM}$) may be calculated:

$A_{v,DM} =- g_m \cdot (r_{o2} \| r_{o4}) =- 20 \frac{mA}{V} \cdot \frac{260 k\Omega \cdot 100 k\Omega}{(260+100) k\Omega} = -1444.4 \frac{v}{v}$

or, in decibels (dB):

$A_{v,DM(dB)} = 20log(|A_{v,DM}|) = 63.2 dB$

### Differential Input Impedance

The differential input impedance of a differential amplifier is the impedance a “seen” by any “differential” signal. A “differential signal” is any and all signals that aren’t shared by $V_{in-}$ and $V_{in+}$.  For instance, if:

$V_{in-} = (2 + sin(2 \pi ft)) V$ and

$V_{in+} = (2 + cos(2 \pi ft)) V$

then the common mode signal and differential mode signals are:

$V_{in,CM} = 2V$ and

$V_{in,DM} = cos(2 \pi ft) - sin(2 \pi ft)$

To find the differential input impedance, begin by following the loop consisting of:

$V_{in-} \rightarrow V_{BE1} \rightarrow -V_{BE2} \rightarrow V_{in+}$, as illustrated below:

We see that, in the differential signal mode, the path to ground only consists of $r_{\pi}$ of each input transistor. Since this is the case, the differential mode input impedance of any BJT diff-amp may be expressed as (omitting emitter resistance and assuming $Q_{1,2}$ matched):

$R_{in,DM} = r_{\pi 1}+r_{\pi 2} = 2r_{\pi}$

where: $r_{\pi} = \frac{\beta}{g_m}$

$\beta = \frac{i_c}{i_b}$ (current gain factor)

A typical value for $\beta$ is 100, and knowing $g_m$ allows one to compute:

$R_{in,DM} = 2 \cdot \frac{\beta}{g_m} = 2 \cdot \frac{100}{20 \frac{mA}{V}} = 10 k \Omega$

So, for the BJT differential amplifier in this tutorial, the differential mode input impedance is:

$R_{in,DM} = 10 k \Omega$ (what impact will this have?)

### Common Mode Gain

The CM gain ($A_{v,CM}$) is the “gain” that common mode signals “see,” or rather, is the attenuation applied to signals present on both differential inputs. A good op amp attempts to eliminate all common mode signals, but this is obviously not possible in the real world.  However, one may compute the common mode gain by “cutting the amplifier in half” by observing one of the loops in the following diagram.  The path differs from that of differential signals because common mode signals make it so that the two signal sources don’t “see” each other.  Notice:

We choose a loop and draw the small-signal model to obtain:

Similar to the output voltage of the differential mode small signal model, we can see that $V_o$ is the voltage across $r_{o4}$.  We also know the current running through this resistance, and may equate the output voltage to:

$V_o = - g_mv_{\pi} \cdot r_{o4}$

This time, though, $v_{in,CM}$ isn’t distributed entirely over the resistances at the base.  Instead, a fraction of the input common mode input signal is across the base-emitter junction.  Referring back to the small signal model, we see that the loop composed of:

$V_{in} \rightarrow v_{\pi2} \rightarrow (i_b + g_mv_{\pi 2}) \cdot 2 \cdot r_{o6}$

reveals that:

$V_{in} = v_{\pi2} + 2 \cdot r_{o6} \cdot (i_b + g_mv_{\pi2})$

but $i_b$ is negligible compared to the current supplied by the collector, so we say:

$V_{in} = v_{\pi2} + 2 \cdot r_{o6} \cdot g_mv_{\pi2} = v_{\pi2} \cdot (1 + 2r_{o6}g_m)$

which we use to solve for $v_{\pi2}$:

$v_{\pi2} =\frac{ v_{in}}{1 + 2 \cdot r_{o6} \cdot g_m}$

Which we then plug back into the equation for $V_o$:

$V_o = - g_mv_{\pi} \cdot r_{o4} = - \frac{r_{o4}g_m}{1+2 \cdot r_{o6} \cdot g_m} \cdot V_{in}$

From this we can solve directly for the common mode gain:

$A_{v,CM} = \frac{V_o}{V_{in}} = -\frac{r_{o4}g_m}{1 + 2r_{o6}g_m}$

Here, the common mode gain is:

$A_{v,CM} = -.3845 = -8.3 dB$

### Common Mode Input Impedance

The common-mode input impedance is the impedance that common-mode input signals “see.” One can analyze the common mode input impedance ($R_{in_{CM}}$) by, again, “cutting the differential amplifier in half” and analyzing one side the resulting schematic, assuming a common mode signal.  This can be found by observing the figure 6, above.

Choosing one of these paths, we construct the corresponding small-signal model for common mode signals (assuming $r_{o2} = \infty$), which is shown in figure 7.  From this figure, deriving $R_{in,CM}$ is simple.  Notice the currents flowing in the loop that consists of:

$V_{in} \rightarrow i_b \cdot r_{\pi2} \rightarrow (i_b + g_mv_{\pi2}) \cdot 2 \cdot r_{o6}$

from this loop, one may compute:

$0 = -V_{in} + i_{b} \cdot r_{\pi 2} + (i_{b} + g_mv_{\pi 2}) \cdot 2\cdot r_{o6}$

which is used to find an equation for $V_{in}$

$V_{in} = i_{b} \cdot r_{\pi 2} + (i_{b} + g_mv_{\pi 2}) \cdot 2\cdot r_{o6}$

and since:

$g_mv_{\pi 2} = \beta \cdot i_{b}$

and $i_b = i_{in}$

So:

$V_{in} = i_b \cdot (r_{\pi 2} + 2 \cdot r_{o6} \cdot ( \beta + 1))$

which is the same as:

$V_{in} = i_{in} \cdot (r_{\pi 2} + 2 \cdot r_{o6} \cdot ( \beta + 1))$

which can be rearranged for:

$R_{in,CM} = \frac{V_{in}}{i_{in}} = r_{\pi 2} + 2 \cdot r_{o6} \cdot (\beta + 1)$

where: $r_{\pi} = \frac{\beta}{g_m}$

Which, in this tutorial, results in:

$R_{in,CM} = r_{\pi 2} + 2 \cdot r_{o6} \cdot (\beta + 1) = \frac{1 mA}{25 mV} + 2 \cdot \frac{130 V}{1 mA} \cdot (100 + 1) = 26.26 M\Omega$

### Common Mode Rejection Ratio (CMRR)

The common mode rejection ratio (CMRR) is simply a ratio of the differential mode gain to the common mode gain, and is defined as:

$CMRR = \frac{A_{v,DM}}{A_{v,CM}}$

Here, the CMRR is:

$CMRR = \frac{-1444.4 v/v}{-.384 v/v} = 3761.46 = 71.5 dB$

### Analysis of FET Differential Amplifiers

As stated before, the analysis of these performance parameters are done virtually the same for FET diff amps as they are for BJT diff amps.  There are, however, a few key differences.  For one, all BJT transistors are typically built to be the same size on a given IC device.  But for an IC device that uses FETs, this is not the case.  Each FET has an adjustable length and width that affects how much current it will pass for a given voltage-drop across the device.  In fact, observe the equation for the drain current in a FET:

$I_D = \frac{k_{n,p}}{2} \frac{W}{L} (|V_{GS}| - |V_{th_{n,p}}|)^2$

From this, the gate-source voltage is:

$V_{GS} = \sqrt{\frac{2I_DL}{kW}} - V_{th_{n,p}}$

where:

• $k$ is the process conductivity parameter, and is equal to:

$k = \mu_{n,p} C_{ox}$ , which is the electron mobility multiplied by the oxide capacitance

• $W, L$ are the width and length of the device, respectively
• $V_{GS}$ is the gate-to-source voltage
• $V_{th}$ is the threshold voltage of the FET

Analyzing BJTs in a circuit is more simple because all base-emitter voltages are assumed to be equal.  But this is not the case for mosfets, and one must analyze the above equation (or others) to find device voltages.  But there is the threshold voltage – the minimum gate-to-source voltage that will allow for any conduction whatsoever.  The threshold voltage is a result of the FET fabrication process, and is typically provided on datasheets for each FET gender.

For a differential amplifier composed of FETs to work, it is imperative that all the FETs be in saturation mode.  For a FET to be in saturation implies:

$|V_{DS}| \ge |V_{GS}| - |V_{th}|$

So this must be checked when analyzing these types of circuits.

Another important difference is the derivation of the transconductance parameter, $g_m$.  When analyzed for a BJT, it was defined as the ratio of the change in collector current to the change in the base-emitter voltage.  For a FET there is a similar procedure, as the transconductance is defined as the ratio of the change in drain current to the change in gate-source voltage.  Mathematically, the transconductance parameter is:

$g_m = \frac{\partial{i_D}}{\partial{v_{GS}}} =\frac{\partial( \frac{k_{n,p}}{2} \frac{W}{L} (|V_{GS}| - |V_{th_{n,p}}|)^2)}{\partial{v_{GS}}} = \sqrt{2I_Dk\frac{W}{L}}$

The last notable difference is the computation for a FET’s small-signal resistance.  The equation describing $r_{o}$ is:

$r_o = \frac{1}{\lambda I_D}$

where $\lambda$ is the channel-length modulation parameter.

From this little discussion, you should be able to apply the principles used to analyze the BJT differential amplifier to the analysis of a FET-based differential amplifier.  But, of course, if you would like to see a FET differential amplifier explained in more detail, do not hesitate to ask a question!

### Credit & Acknowledgment

This post was created in March 2011 by Kansas State University Electrical Engineering student Safa Khamis.  A million thank yous extended to Safa for taking the time to document this important process for everyone else to learn from.  Please leave questions, comments, or ask a question in the questions section of the website.

$V_A_n = \frac{V_A_n}{I_C} = \frac{130 V}{.5 mA} = 260 k\Omega$ $V_A_n = \frac{V_A_n}{I_C} = \frac{130 V}{.5 mA} = 260 k\Omega$

## 2 Replies to “DC Biasing & AC Performance Analysis of BJT & FET Differential Amplifiers”

1. Paul says:

Hi,
Perhaps just a quick explanation on the input impedance for the MOSFET case?
Thanks

1. Hi Paul, sorry for the late response, but we’ve been quite busy lately. Unfortunately I don’t have time to put this together right now. But I can offer some tips here in paragraph form. You’ll want to grab a book, or Google to reference these terms if you aren’t familiar.

Consider a MOSFET amplifier schematic diagram. If you want to determine the total equivalent input capacitance (gate to small-signal ground..this should help you draw it), you need to first combine all resistors that you can on the input of the amplifier (Vs+). If you reference the BJT explanation, you will see how the schematics are laid out. You should follow this same method for drawing your MOSFET amplifier circuit.

Connected to the source (Vs+) is a resistor (Rs=47k), in series. Rs is connected horizontally to two parallel resistors (R1=22k) & (R2=33k) which can be combined together to an equivalent 13.2k connected to R(s) down to ground.

In parallel with this R1||R2 combined resistor we’ve made, we have two parallel capacitances that give rise. These are present on both the input and the output of the amplifier and are called the Miller Capacitors. I won’t go into calculating those, but to calculate the purely resistive input impedance, combine your 13.2k with Rs.

Hope this helps a little.